https://northwood.blog.fc2.com/blog-entry-10791.html
Mon, Mar 01, 2021
AMD "Zen 4" Microarchitecture to Support AVX-512 (techPowerUp!)
AMD Zen4 core in EPYC "Genoa" may support AVX3-512 instructions (VideoCardz)
AMD EPYC Genoa Zen 4 CPUs Rumored To Feature AVX3-512 & BFLOAT16 Instruction Sets, Firing Back at Intel Xeons (WCCF Tech)
[CPU] [rumor] A picture of Zen4 Genoa I saw in Post Bar, avx512?
AMD's next CPU architecture, "Zen 4", will be used for the 4th generation EPYC, "Genoa", etc. This "Zen 4 This is the first CPU microarchitecture from AMD to support 512-bit AVX instructions. However, the extent to which special instruction groups within the AVX-512 instruction set will be supported will be confirmed in the future. It is also expected that the AVX-512 instructions implemented in "Zen 4" will be supported by all processors using the "Zen 4" architecture - including enterprise-oriented It remains to be seen whether EPYC to client Ryzen will be enabled in the same way, or whether the direction will be similar to that of Intel, with only a few instructions for the client.
The source of the information is Chiphell's Forum.
AMD Zen 4 AVX-512 (March 1, 2021)
The image appears to be a cutout of a slide, which contains the contents of this issue. The image shows the features of "Zen 4" as follows.
More than 64-cores per socket.
2-threads per core
Supports configurations up to 2-socket
57-bit virtual address, 52-bit physical address
AVX3-512, BFloat 16, and other instruction set implementations
Improved performance and performance per watt through design and manufacturing improvements
AVX-512 has been available from Intel since "Skylake-SP" for Xeon, from "Ice Lake-U" for consumer mobile and from "Ice Lake-U" for desktop. (Strictly speaking, the Mobile version has been available since "Cannon Lake-U," when only the Core i3 8121U was available.)
AMD has been holding off on implementing the AVX-512 instruction until now, but the next "Zen 4" will finally implement the AVX-512 instruction. The AVX-512 instruction covers a wide range of content, so it will be necessary to confirm the extent of the implementation in the future. There is also a high possibility that some changes will be made to the floating-point arithmetic unit on the hardware side in order to support the AVX-512 instructions.
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